Characterization of CMOS Fully Differential Amplifiers for Automatic Design Procedure

This paper presents the design and characterization of fully differential amplifiers for application in an automatic circuit sizing tool. The tool uses Simulated Annealing as main optimization heuristic and electrical simulations for circuit specifications evaluations. The methodology is based on the minimization of a cost function and a set of constraints in order to size each transistor of the circuit. A set of standard testbenches are implemented in the tool to estimate the specifications values. In these testbenches an ideal commonmode feedback (CMFB) circuit is used. As design example, this paper shows the application of the approach for the design of a single-stage fully differential amplifier in 0.18 μm technology. The results show that all required specifications are met in an acceptable execution time.